Field of the Invention
The present invention relates to a power semiconductor device.
Description of the Background Art
A power semiconductor device functions as a power module supplying high power. The power semiconductor device is used for an inverter drive as one of main purposes. The power semiconductor device used for the inverter drive includes a plurality of power chips and an integrated circuit (IC) driving each of the power chips. The power chips are power semiconductor chips.
Miniaturization of an area of a substrate in the power semiconductor device and cost reduction are required for the power semiconductor device.
Japanese Patent Application Laid-Open No. 2012-074720 discloses a technique for reducing a size of the power semiconductor device (hereinafter, also referred to as a related technique A). Specifically, the related technique A discloses a technique for suitably packaging power chips and a control IC into one. The power chips are metal oxide semiconductor field effect transistors (MOSFETs). Japanese Patent Application Laid-Open No. 2012-074720 discloses the quad flat package (QFP) packaging power chips and control ICs with a use of the related technique A.
Unfortunately, the related technique A has problems. Specifically, in the related technique A, all of the power chips included in the power semiconductor device are intensively disposed close to one another in the package.
For this reason, in the related technique A, thermal interference between the power chips generating heat is conspicuous. As a result, in the related technique A, each power chip has extremely poor thermal dissipation properties. In other words, it is necessary to suppress the thermal interference between the power chips to improve the thermal dissipation properties of the power chips.